计算机体系结构与芯片组设计方向博士职位

PhD Position F/M Multi-Level Multi-Objective Design Space Exploration for Chiplet-Based Systems

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Contract type : Fixed-term contract

Level of qualifications required : Graduate degree or equivalent

Fonction : PhD Position

About the research centre or Inria department

The Inria Centre at Rennes University is one of Inria's nine centres and has more than thirty research teams. The Inria Centre is a major and recognized player in the field of digital sciences. It is at the heart of a rich R&D and innovation ecosystem: highly innovative PMEs, large industrial groups, competitiveness clusters, research and higher education players, laboratories of excellence, technological research institute, etc.

Context

The PhD will be led by Inria Rennes, in close collaboration with CEA under the PEPR ChipMosaic - Phoenix

Additional information about the city and the university

Rennes is a vibrant and student-friendly city in northwestern France. The city has a thriving student culture, with plenty of bars, restaurants, cultural events, and an affordable cost of living. Additionally, Rennes is evaluated as one of the best cities to live in Europe .

Rennes is home to the University of Rennes, one of the largest universities in France. The University of Rennes has a strong focus on innovation and technology. It is home to many world-renowned research institutes, including INSA, IRISA, and INRIA Rennes. These institutes offer a wide range of Ph.D. programs in computer science, covering various topics such as artificial intelligence, machine learning, data science, and hardware and software engineering. Ph.D. students in Rennes benefit from close relationships with faculty and access to state-of-the-art facilities. The students also have the opportunity to collaborate with leading researchers worldwide.

Team’s LinkedIn page: TARAN's LinkedIn

Team’s webpage: TARAN

Assignment

The slowing of Moore’s Law and the escalating costs of monolithic chip manufacturing have positioned chiplet-based architectures as the dominant paradigm for future systems. A chiplet-based architecture consists of the modular integration of multiple System-on-Chip (SoC) dies to improve computing performance, integration density, and memory capacity while maximizing silicon utilization by leveraging heterogeneous semiconductor process technologies. It is based on the assembly of specialized functional components – including CPU and GPU cores, memory modules, and domain-specific accelerators – within a unified system. This modular paradigm enables the efficient design of increasingly complex architectures through the composition of reusable and independently optimized building blocks. This design approach offers unprecedented flexibility, scalability, and cost-effectiveness. The heterogeneous integration enabled by chiplets further allows designers to combine the most suitable process technologies for each function—for instance, using advanced nodes for compute chiplets while relying on more mature, cost-effective nodes for I/O and memory functions.

However, this modularity comes at the cost of an explosion in design complexity: the design space now encompasses not only traditional core-level and memory hierarchy parameters but also chiplet composition, inter-chiplet communication fabrics, packaging technologies (2.5D interposers, bridges, 3D stacking), and thermal management strategies. Furthermore, system integrators must consider the diverse characteristics of chiplets from multiple vendors, each with different performance, power, area, and reliability profiles. This multidimensional design space renders traditional exploration approaches computationally intractable.

Existing DSE methodologies exhibit several critical limitations when applied to chiplet-based systems. Traditional cycle-accurate simulation is infeasible for large-scale multi-chiplet systems due to host-machine performance and memory limitations. There is no unified framework that integrates the diverse tools needed for chiplet-level, inter-chiplet, and package-level evaluation. Designers must manually navigate between architectural simulators, thermal models, communication network simulators, and packaging analysis tools, leading potential inconsistencies in evaluation. Most approaches focus on one or two objectives (typically performance and power), neglecting area, cost, thermal, and real-tima and aging metrics. Few frameworks support the co-exploration of architecture, mapping, and packaging decisions in an integrated manner. Design choices—such as which chiplets to include, how to distribute workload across them, and how to package them—are deeply interdependent, yet existing approaches often treat them sequentially or in isolation.

Main activities

This thesis proposes novel approaches for Design Space Exploration to address the unique challenges of chiplet-based system design. The research will propose a DSE methodology that combines multifidelity simulation tools, analytical models, and advanced multi-objective optimization algorithms to explore the vast design space of chiplet-based architectures. To achieve that, it establishes a formal modelling framework to capture hierarchical interdependencies across core, chiplet, inter-chiplet design parameters. Second, it develops a multi-fidelity evaluation strategy integrating heterogeneous simulation tools—combining fast virtual prototyping with detailed models (thermal, power, communication, and timing)—for fast yet accurate early-stage exploration. Third, it adapts multi-objective optimization algorithms, including genetic algorithms and reinforcement learning, to navigate the vast heterogeneous design space, with novel techniques tailored to the hierarchical nature of chiplet design. The framework will be validated on representative workloads, demonstrating significant improvements in power, performance, area, but also thermal, aging and real-time metrics compared to state-of-the-art approaches.

Skills

Candidate Profile

The candidate should have a strong background in one or more of the following areas:

• Computer architecture

• Design Space Exploration approaches

• Operations Research & Combinatorial Optimization and algorithms

Good programming skills are expected, preferably in C/C++, and Python.

Experience with architectural simulators, such as GEM5, and low-level systems programming would be an advantage.

Languages : proficiency in written English and fluency in spoken English. The interviews for the PhD will be in English.

Relational skills : the candidate will work in a research team, where regular meetings will be set up. The candidate has to be able to present the progress of their work in a clear and detailed manner.

Other values appreciated : Open-mindedness, strong integration skills, and team spirit.

Most importantly, we seek highly motivated candidates.

Benefits package

• Subsidized meals

• Partial reimbursement of public transport costs

• Leave: 7 weeks of annual leave + 10 extra days off due to RTT (statutory reduction in working hours) + possibility of exceptional leave (sick children, moving home, etc.)

• Possibility of teleworking (after 6 months of employment) and flexible organization of working hours

• Professional equipment available (videoconferencing, loan of computer equipment, etc.)

• Social, cultural and sports events and activities

• Access to vocational training

Remuneration

monthly gross salary 2300 euros

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General Information

• Theme/Domain : Architecture, Languages and Compilation

System & Networks (BAP E)

• Town/city : Rennes

• Inria Center :

Centre Inria de l'Université de Rennes

• Starting date : 2027-04-01

• Duration of contract : 3 years

• Deadline to apply : 2026-12-31

Warning : you must enter your e-mail address in order to save your application to Inria. Applications must be submitted online on the Inria website. Processing of applications sent from other channels is not guaranteed.

Instruction to apply

Please submit online : your resume, cover letter and letters of recommendation eventually

Defence Security :

This position is likely to be situated in a restricted area (ZRR), as defined in Decree No. 2011-1425 relating to the protection of national scientific and technical potential (PPST).Authorisation to enter an area is granted by the director of the unit, following a favourable Ministerial decision, as defined in the decree of 3 July 2012 relating to the PPST. An unfavourable Ministerial decision in respect of a position situated in a ZRR would result in the cancellation of the appointment.

Recruitment Policy :

As part of its diversity policy, all Inria positions are accessible to people with disabilities.

Contacts

• Inria Team :

TARAN

• PhD Supervisor :

Kritikakou Angeliki / angeliki.kritikakou@irisa.fr

About Inria

Inria, the French national institute for research in digital science and technology, supports the French government in national research and innovation strategies in the digital field, acting as Digital Programs Agency. Inria leads over 300 research and innovation projects with its 3,500 scientists, engineers, and support staff, in partnership with universities and the digital ecosystem (businesses, entrepreneurs, and public stakeholders). Together, we explore strategic fields such as artificial intelligence, cybersecurity, quantum computing, cloud technologies, digital transformation in healthcare, digital twins, and digital technologies for defence. We develop practical solutions such as software, tech startups, partnerships with national companies, and cutting-edge training programmes. Our goal is to drive scientific, technological, and industrial excellence to ensure France’s digital sovereignty.